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CY7C1021B CY7C10211B
1-Mbit (64K x 16) Static RAM
Features
* Temperature Ranges -- Commercial: 0C to 70C -- Industrial: -40C to 85C -- Automotive: -40C to 125C * High speed -- tAA = 10 ns (Commercial & Industrial) -- tAA = 15 ns (Automotive) * CMOS for optimum speed/power * Low active power -- 825 mW (max.) * Automatic power-down when deselected * Independent control of upper and lower bits * Available in 44-pin TSOP II and 400-mil SOJ * Also available in Lead (Pb)-Free 44-pin TSOP II Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021B/10211B is available in standard 44-pin TSOP Type II and 400-mil-wide SOJ packages. Customers should use part number CY7C10211B when ordering parts with 10-ns tAA, and CY7C1021B when ordering 12- and 15-ns tAA.
Functional Description[1]
The CY7C1021B/10211B is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.
Logic Block Diagram
DATA IN DRIVERS
A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
64K x 16 RAM Array 512 X 2048
SENSE AMPS
I/O1-I/O8 I/O9-I/O16
COLUMN DECODER BHE WE CE OE BLE
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05145 Rev. *A
*
A8 A9 A10 A11 A12 A13 A14 A15
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised June 20, 2004
CY7C1021B CY7C10211B
Selection Guide
7C10211B-10 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Com'l / Ind'l Automotive Com'l / Ind'l Automotive L Version 10 150 10 0.5 7C1021B-12 12 140 10 0.5 7C1021B-15 15 130 150 10 15 0.5
Pin Configurations
SOJ / TSOP II Top View A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
Pin Definitions
Pin Name A0-A15 I/O1-I/O16 NC WE CE BHE, BLE OE SOJ, TSOP-Pin Number 1-5,18-21, 24-27, 42-44 7-10, 13-16, 29-32, 35-38 22, 23, 28 17 6 39, 40 41 I/O Type Input Description Address Inputs used to select one of the address locations.
Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation. No Connect No Connects. Not connected to the die. Input/Control Write Enable Input, active LOW. When selected LOW, a Write is conducted. When deselected HIGH, a Read is conducted. Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input/Control Byte Write Select Inputs, active LOW. BLE controls I/O8-I/O1, BHE controls I/O16-I/O9. Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system.
VSS VCC
12, 34 11, 33
Power Supply Power Supply inputs to the device.
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CY7C1021B CY7C10211B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[2] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ......................................-0.5V to VCC+0.5V DC Input Voltage[2] ...................................-0.5V to VCC+0.5V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Automotive Ambient Temperature (TA)[3] 0C to +70C -40C to +85C -40C to +125C VCC 5V 10% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current Output Leakage Current Output Short Circuit Current[4] VCC Operating Supply Current Automatic CE Power-Down Current--TTL Inputs GND < VI < VCC GND < VI < VCC, Output Disabled Com'l / Ind'l Automotive Com'l / Ind'l Automotive Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -1 -1 7C10211B-10 7C1021B-12 Min. 2.4 0.4 6.0 0.8 +1 +1 -300 150 40 10 0.5 2.2 -0.5 -1 -1 Max. Min. 2.4 0.4 6.0 0.8 +1 +1 -300 140 40 10 0.5 2.2 -0.5 -1 -4 -1 -4 Max. 7C1021B-15 Min. 2.4 0.4 6.0 0.8 +1 +4 +1 +4 -300 130 150 40 50 10 15 0.5 Max. Unit V V V V A A A A mA mA mA mA mA mA mA mA
VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com'l / Ind'l Automotive
Max. VCC, CE > VIH Com'l / Ind'l VIN > VIH or VIN < VIL, f Automotive = fMAX
ISB2
Automatic CE Max. VCC, CE > VCC - Com'l / Ind'l Power-Down 0.3V, VIN > VCC - 0.3V, Automotive Current--CMOS or VIN < 0.3V, f = 0 Inputs L Version
Thermal Resistance[5]
Parameter Description Test Conditions 44-lead SOJ 64.32 31.03 44-lead TSOP-II 76.89 14.28 Unit C/W C/W
JA JC
Thermal Resistance Test conditions follow standard test methods and (Junction to Ambient) procedures for measuring thermal impedance, Thermal Resistance per EIA / JESD51. (Junction to Case)
Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 3. TA is the "Instant On" case temperature. 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters.
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CY7C1021B CY7C10211B
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) Equivalent to: OUTPUT THEVENIN EQUIVALENT R2 255 R 481 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) 167 30 pF 1.73V R2 255 GND
Rise Time: 1 V/ns
R 481
3.0V
ALL INPUT PULSES 90% 10% 90% 10%
Fall Time:1 V/ns
Switching Characteristics[6] Over the Operating Range
7C10211B-10 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[9] tWC tSCE tAW tHA tSA tSD tHD Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start Data Set-Up to Write End Data Hold from Write End 10 8 7 0 0 5 0 12 9 8 0 0 6 0 15 10 10 0 0 8 0 ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[7] OE HIGH to High CE LOW to Low Z[7, 8] 3 5 0 10 5 0 5 0 6 0 12 6 0 7 Z[7] 0 5 3 6 0 15 7 3 10 5 0 6 3 7 10 10 3 12 6 0 7 12 12 3 15 7 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C1021B-12 Min. Max. 7C1021B-15 Min. Max. Unit
CE HIGH to High Z[7, 8] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z
Notes: 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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CY7C1021B CY7C10211B
Switching Characteristics[6] Over the Operating Range (continued)
7C10211B-10 Parameter tLZWE tHZWE tBW Description WE HIGH to Low Z[7] WE LOW to High Z
[7, 8]
7C1021B-12 Min. 3 Max. 6 8
7C1021B-15 Min. 3 7 9 Max. Unit ns ns ns
Min. 3
Max. 5
Byte Enable to End of Write
7
Switching Waveforms
Read Cycle No. 1 [10, 11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled) [11, 12]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE
HIGH IMPEDANCE
IICC CC IISB SB
Notes: 10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 11. WE is HIGH for read cycle.
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CY7C1021B CY7C10211B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled) [13, 14]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE t BW BHE, BLE tSD DATA I/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O
Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
tHA
tHD
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CY7C1021B CY7C10211B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOW)
tWC ADDRESS
CE
tSCE
tAW tSA WE tBW BHE, BLE tHZWE DATA I/O tSD tHD tPWE
tHA
tLZWE
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1-I/O8 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O9-I/O16 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power-Down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C10211B-10VC CY7C10211B-10ZC CY7C10211BL-10ZC 12 CY7C1021B-12VC CY7C1021B-12VI CY7C1021BL-12VC CY7C1021B-12ZC CY7C1021B-12ZI CY7C1021BL-12ZC Package Name V34 Z44 Z44 V34 V34 V34 Z44 Z44 Z44 Package Type 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead TSOP Type II Operating Range Commercial Commercial Commercial Commercial Industrial Commercial Commercial Industrial Commercial
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CY7C1021B CY7C10211B
Ordering Information (continued)
Speed (ns) 15 Ordering Code CY7C1021B-15VC CY7C1021B-15VI CY7C1021BL-15VC CY7C1021B-15VE CY7C1021B-15ZC CY7C1021B-15ZXC CY7C1021B-15ZI CY7C1021BL-15ZC CY7C1021B-15ZE Package Name V34 V34 V34 V34 Z44 Z44 Z44 Z44 Z44 Package Type 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ 44-pin (400-Mil) Molded SOJ 44-pin TSOP Type II Lead (Pb)-Free, 44-pin TSOP Type II 44-pin TSOP Type II 44-pin TSOP Type II 44-pin TSOP Type II Operating Range Commercial Industrial Commercial Automotive Commercial Commercial Industrial Commercial Automotive
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
44 23
DIMENSIONS IN INCHES MIN. MAX.
0.395 0.405 0.435 0.445
1
22
SEATING PLANE 1.120 1.130 0.095 0.115 0.023 0.033 0.013 0.023
0.128 0.148 0.004 0.025 MIN.
0.082 MIN. 0.365 0.375
0.007 0.013
0.045 MAX.
0.050 TYP.
0-10
51-85082-*B
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CY7C1021B CY7C10211B
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1021B CY7C10211B
Document History Page
Document Title: CY7C1021B/CY7C10211B 64K x 16 Static RAM Document Number: 38-05145 REV. ** *A ECN NO. Issue Date 109889 238454 09/22/01 See ECN Orig. of Change SZV RKF Description of Change Change from Spec number: 38-00951 to 38-05145 1) Added Automotive Specs to Data Sheet 2) Added Pb-Free device offering in the Ordering Information
Document #: 38-05145 Rev. *A
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